A possible AMD EPYC 7004 ‘Genoa’ CPU engineering sample has been spotted within Geekebench 5 database. The sample doesn’t provide us with much information if its truly a Genoa chip but there’s one aspect that may confirm that it might indeed be the case.
AMD 5nm EPYC 7004 ‘Genoa’ CPU Engineering Spotted Within Geekbench 5: Features 32 Zen 4 Cores, 32 MB L2 Cache, 128 MB L3 Cache & Up To 4.6 GHz Clocks
The leaked chip is identified as an AMD Engineering sample with the ‘100-000000866-01’ codename and it looks very much like an upgraded version of the previous Genoa sample that leaked out back in March.
This specific AMD EPYC Genoa chip is fabricated on the 5nm process node and will rock a total of 32 Zen 4 cores and 64 threads. In terms of clock speeds, the CPU is reported to feature a base clock of 1.20 GHz while the all-core boost is rated at 4.60 GHz.
This is an increase of 35% over the previous chip which was running at a max clock speed of 3.4 GHz. Now, these are preliminary clock speeds and we can’t say for sure how well those clocks were being maintained throughout the tests. Our guess is not that good considering the lower scores compared to the 3.4 GHz sample.
As for the cache, the L3 cache remains 32 MB per CCD and this 32 core chip packs four Zen 4 CCDs which will give 128 MB of L3 cache. The L2 cache on the other hand sees a huge bump with a 2x increase over the current Zen 3 design. The AMD EPYC Genoa CPU packs 1 MB of L2 cache per core so that’s 32 MB of L2 cache on the chip whereas a 32 core variant within the Zen 3 lineup would feature only 16 MB of L2 cache. Do note that this is only a four-chiplet chip since the flagship Genoa chips will carry as many as 12 chiplets for a total of 96 MB L2 cache.
The platform featured 384 GB of memory which should be DDR5 since Genoa rocks a DDR5 IMC rather than DDR4 on existing Zen 3 EPYC CPUs. The Pegatron platform it was tested on featured NVIDIA’s A100 80 GB PCIe accelerators. The AMD EPYC Genoa CPUs based on the 5nm process node will be offering up to 96 cores when they land on the new SP5 platform later this year. We are expecting some huge improvement in both single and multi-core performance and this leak is evident of that.
AMD EPYC CPU Families:
|Family Name||AMD EPYC Naples||AMD EPYC Rome||AMD EPYC Milan||AMD EPYC Milan-X||AMD EPYC Genoa||AMD EPYC Bergamo||AMD EPYC Turin||AMD EPYC Venice|
|Family Branding||EPYC 7001||EPYC 7002||EPYC 7003||EPYC 7003X?||EPYC 7004?||EPYC 7005?||EPYC 7006?||EPYC 7007?|
|CPU Architecture||Zen 1||Zen 2||Zen 3||Zen 3||Zen 4||Zen 4C||Zen 5||Zen 6?|
|Process Node||14nm GloFo||7nm TSMC||7nm TSMC||7nm TSMC||5nm TSMC||5nm TSMC||3nm TSMC?||TBD|
|Socket||LGA 4094||LGA 4094||LGA 4094||LGA 4094||LGA 6096||LGA 6096||LGA 6096||TBD|
|Max Core Count||32||64||64||64||96||128||256||384?|
|Max Thread Count||64||128||128||128||192||256||512||768?|
|Max L3 cache||64 MB||256 MB||256 MB||768 MB?||384 MB?||TBD||TBD||TBD|
|Chiplet Design||4 CCD’s (2 CCX’s per CCD)||8 CCD’s (2 CCX’s per CCD) + 1 IOD||8 CCD’s (1 CCX per CCD) + 1 IOD||8 CCD’s with 3D V-Cache (1 CCX per CCD) + 1 IOD||12 CCD’s (1 CCX per CCD) + 1 IOD||12 CCD’s (1 CCX per CCD) + 1 IOD||TBD||TBD|
|Memory Channels||8 Channel||8 Channel||8 Channel||8 Channel||12 Channel||12 Channel||TBD||TBD|
|PCIe Gen Support||64 Gen 3||128 Gen 4||128 Gen 4||128 Gen 4||128 Gen 5||TBD||TBD||TBD|
|TDP Range||200W||280W||280W||280W||320W (cTDP 400W)||320W (cTDP 400W)||480W (cTDP 600W)||TBD|
News Source: Benchleaks