A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors

Researchers propose DarkGates, a hybrid system architecture that increases the performance of Fmax-constrained systems while fulfilling their power efficiency requirements.

New research paper from ETH Zurich and others.

Abstract
“To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components’ power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system’s power-delivery impedance and voltage guardband, limiting the system’s maximum attainable voltage (ie, Vmax) and, thus, the CPU core’s maximum attainable frequency (ie, Fmax). As a result, systems that are performance constrained by the CPU frequency (ie, Fmax-constrained), such as high-end desktops, suffers significant performance loss due to power-gates.

To mitigate this performance loss, we propose DarkGates, a hybrid system architecture that increases the performance of Fmax-constrained systems while fulfilling their power efficiency requirements. DarkGates is based on three key techniques: i) bypassing on-chip power-gates using package-level resources (called bypass mode), ii) extending power management firmware to support operation either in bypass mode or normal mode, and iii) deeper introduction idle power states.

We implement DarkGates on an Intel Skylake microprocessor for client devices and evaluate it using a wide variety of workloads. On a real 4-core Skylake system with integrated graphics, DarkGates improves the average performance of SPEC CPU2006 workloads across all thermal design power (TDP) levels (35W-91W) between 4.2% and 5.3%. DarkGates maintains the performance of 3DMark workloads for desktop systems with TDP greater than 45W while for a 35W-TDP (the lowest TDP) desktop it experiences only a 2% degradation. In addition, DarkGates fulfills the requirements of the ENERGY STAR and the Intel Ready Mode energy efficiency benchmarks of desktop systems.”

Find the technical paper link here or here . Published 12/2021.

Jawad Haj Yahya, Jeremy S. Kim, A. Giray Yaglikci, Jisung Park, Efraim Rotem, Yanos Sazeides, Onur Mutlu.

Visit Semiconductor Engineering’s Technical Paper library here and discover many more chip industry academic papers.

Leave a Reply

%d bloggers like this: